1. Field
This disclosure relates generally to data processing systems, and more specifically, to error detection schemes for use in a cache.
2. Related Art
Data caches and instruction caches are typically used in data processing systems. Error detection for these caches improves reliability. Error detection code (EDC), error correction code (ECC), and parity protection types are commonly used to provide error detection and/or error correction for memories. However, the use of EDC/ECC for caches may be problematic, especially for level 1 (L1) caches which have more critical timing constraints than higher level caches. That is, although EDC or ECC typically supports a higher level of error detection as compared to using parity, complexity of the cache is greatly increased and the performance is reduced. In some cases, a higher emphasis is placed on error detection where some performance can be sacrificed to obtain a certain level of safety certification. However, in other cases, it is not possible or desirable to sacrifice performance for additional error detection capabilities. These conflicting needs further increases the difficulties faced when designing caches.